1. Field
Example embodiments relate to a cell structure for a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a cell structure for a semiconductor memory device including a 6F2 unit structure and a method of fabricating the same.
2. Description of the Related Art
The size of unit cells of semiconductor memory devices may be reduced due to increasingly smaller or minute design rules, as integration degrees of the memory devices increase. Cell structures of dynamic random-access memory (DRAM) devices have been shifting from an 8F2 unit cell structure to a 6F2 unit cell structure, so as to satisfy the higher integration degrees of the memory devices. Shifting from the 8F2 unit cell structure to the 6F2 unit cell structure may cause various processing problems, as follows.
FIG. 1 is a diagram illustrating a cell structure of a conventional semiconductor memory device including an 8F2 unit cell. Referring to FIG. 1, an active region 10 of the conventional semiconductor memory device including the 8F2 unit cell may make contact with a lower electrode contact pad 12 at both end portions thereof and may make contact with a bit-line contact pad 14 at a central portion thereof. Both end portions of the active region 10 may be referred to as a first area of a substrate, and the central portion of the active region 10 may be referred to as a second area of the substrate. The active region 10 may have an elliptical shape defined by a major axis and a minor axis, and the major axis of the active region 10 may have a length of about 5F and the minor axis of the active region 10 may have a length of about 1F. The capital letter ‘F’ denotes a minimized or decreased line width of the semiconductor memory device and each of lattices in FIG. 1 occupies an area of the substrate as large as 1F×1F. A longitudinal array of the lattices of the substrate may be referred to as a lattice row, and a latitudinal array of the lattices of the substrate may be referred to as a lattice column.
In the cell structure of the conventional memory device including the 8F2 unit cell, the active region 10 may be repeatedly positioned in a direction of the lattice row and spaced apart by a predetermined or given distance from an adjacent active region. The active region 10 may be also repeatedly positioned in a direction of the lattice column under the condition that the centers of the repeated active regions 10 are on the same line, so that the active regions have the same central axis in the direction of the lattice column. The major axis of the active region 10 may be parallel with the lattice row of the substrate and the minor axis of the active region 10 may be parallel with the lattice column of the substrate. A space between the active regions 10 of the substrate may be referred to as a third area of the substrate.
The lower electrode contact pad 12 may be positioned on the first area of the substrate and may make contact with the active region 10, and the bit-line contact pad 14 may be positioned on the second area of the substrate and may make contact with the active region 10. The bit-line contact pad 14 may cross the second area and the third area of the substrate, so that a first portion of the bit-line contact pad 14 may be positioned in the second area of the substrate, and a second portion of the bit-line contact pad 14 may be positioned in the third area of the substrate. The third area of the substrate may correspond to a field region for defining the active region and also may have a length of about 1F.
A gate pattern 16 may be positioned on a gap area between the first and second areas of the active region 10 as a word line of the memory device. The gate pattern 16 may be repeatedly positioned between the upper electrode contact pad 12 and the bit-line contact pad 14 in a direction of the minor axis. A bit line 18 may be positioned in the third area of the substrate, so that the second portion of the bit-line contact pad 14 may make contact with the bit line 18 in the third area of the substrate. A unit cell of a memory cell structure may be classified on the basis of a lower electrode. The lower electrode contact pad 12, which makes contact with the lower electrode, may occupy a lattice area of 4F×2F as shown in FIG. 1, so that the cell structure of the memory cell may include the 8F2 unit cell 20.
FIG. 2 is a diagram illustrating a cell structure of a conventional semiconductor memory device including a 6F2 unit cell. Referring to FIG. 2, an active region 30 of the conventional semiconductor memory device including the 6F2 unit cell may make contact with a lower electrode contact pad 32 at both end portions thereof and may make contact with a bit-line contact pad 34 at a central portion thereof. Both end portions of the active region 30 may be referred to as a first area of a substrate, and the central portion of the active region 30 may be referred to as a second area of the substrate. The active region 30 may have an elliptical shape defined by a major axis and a minor axis, and the major axis of the active region 10 may have a length of about 5F, and the minor axis of the active region 30 may have a length of about 1F. In the same way as the cell structure including the 8F2 unit cell, the capital letter ‘F’ may denote a minimized or decreased line width of the semiconductor memory device and each of lattices in FIG. 2 may occupy an area of the substrate that may be about 1F×1F.
A longitudinal array of the lattices of the substrate may be referred to as a lattice row and a latitudinal array of the lattices of the substrate may be referred to as a lattice column. In the cell structure of the conventional memory device including the 6F2 unit cell, the active region 30 may be repeatedly positioned in an oblique direction that is inclined at a predetermined or given angle with respect to the lattice row and spaced apart by a predetermined or given distance from an adjacent active region in the oblique direction. The end portions of the active region 30 may be positioned on the lattice rows different from each other symmetrically with respect to the second portion of the substrate, and the major axis of the active region 30 may be also inclined at the angle with respect to the lattice row of the substrate. A space between the active regions 30 on the substrate may be referred to as a third area of the substrate.
The cell structure of the memory device including the 6F2 unit cell may be the same as that of the memory device including the 8F2 unit cell except for the configuration of the active region 30 and the bit-line contact pad 34. The lower electrode contact pad 32 may be positioned on the first area of the substrate and may make contact with the active region 30, and the bit-line contact pad 34 may be positioned on the second area of the substrate and may make contact with the active region 30. The bit-line contact pad 34 may not cross the second area and the third area of the substrate and may only be positioned on the second area of the substrate. The cell structure including the 6F2 unit cell may have improved space usage as compared with the cell structure including the 8F2 unit cell. The third area of the substrate may correspond to a field region for defining the active region 30 and also may have a length of about 1F.
A gate pattern 36 may be positioned on a gap area between the first and second areas of the active region 30 as a word line of the memory device. The gate pattern 36 may be repeatedly positioned between the upper electrode contact pad 32 and the bit-line contact pad 34 in a direction of the lattice column of the substrate. A bit line 38 may be positioned in the third area of the substrate in a direction of the lattice row of the substrate, and may make contact with the bit-line contact pad 34.
As described above, a unit cell of a memory cell structure may be classified on the basis of a lower electrode. The lower electrode contact pad 32, which may make contact with the lower electrode, may occupy a lattice area of about 3F×2F as shown in FIG. 2, so that the cell structure of the memory cell may include the 6F2 unit cell 40. Hereinafter, the cell structure of the memory cell including the 8F2 unit cell 20 may be referred to as an 8F2 cell structure, and the cell structure of the memory cell including the 6F2 unit cell 40 may be referred to as a 6F2 cell structure.
The 6F2 cell structure may be desirable at a higher integration degree as compared with the 8F2 cell structure due to the improved space usage of the 6F2 cell structure. The 6F2 cell structure may be undesirable in a process for manufacturing the memory device due to the oblique arrangement of the active region 30. For example, a photolithography process may be relatively difficult to be performed on the substrate due to the requirement of the oblique arrangement of the active region 30.
The oblique arrangement of the active region 30 may require an asymmetrical illumination system corresponding to an inclination angle in the photolithography process, and the active region 30 necessarily may include several segments. Optical proximity correction (OPC) of the illumination may be relatively deteriorated, not at the cell area but at the peripheral area of the substrate due to the asymmetry of the illumination system. The field region of the substrate may become relatively non-uniform because several segments may constitute the active region 30. For the above reasons, the 6F2 cell structure may have not been used as a cell structure of a memory device despite improved space usage thereof as compared with the 8F2 cell structure.